voron

experimental ARM OS
git clone git://git.2f30.org/voron.git
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commit b4990f01971abc97e9529bc43e285e26172d22f0
parent 6d38b9553bddefedb206156197232d24eaed6d73
Author: oblique <psyberbits@gmail.com>
Date:   Sat Apr 20 12:47:29 +0300

mmu.c: add dsb after every TLB invalidation

this ensures that invalidation completed.

Diffstat:
kernel/mmu.c | 13+++++++++----
1 file changed, 9 insertions(+), 4 deletions(-)
diff --git a/kernel/mmu.c b/kernel/mmu.c @@ -15,9 +15,10 @@ mmu_init(void) asm volatile ( /* invalidate TLB - * v1 is ignored - */ + * v1 is ignored */ "mcr p15, 0, v1, c8, c7, 0 \n\t" + /* completes the TLB invalidation */ + "dsb \n\t" /* set TTBCR */ "mov v1, #0 \n\t" "mcr p15, 0, v1, c2, c0, 2 \n\t" @@ -29,6 +30,8 @@ mmu_init(void) "mcr p15, 0, v1, c3, c0, 0 \n\t" /* invalidate TLB */ "mcr p15, 0, v1, c8, c7, 0 \n\t" + /* completes the TLB invalidation */ + "dsb \n\t" /* enable AFE */ "mrc p15, 0, v1, c1, c0, 0 \n\t" "orr v1, v1, #(1 << 29) \n\t" @@ -43,13 +46,14 @@ mmu_enable(void) asm volatile ( /* invalidate TLB */ "mcr p15, 0, v1, c8, c7, 0 \n\t" + /* completes the TLB invalidation */ + "dsb \n\t" /* enable MMU */ "mrc p15, 0, v1, c1, c0, 0 \n\t" "orr v1, v1, #1 \n\t" "mcr p15, 0, v1, c1, c0, 0 \n\t" : : : "v1" ); - dsb(); } void @@ -185,7 +189,8 @@ mmu_map_page(void *phys, void *virt, uint_t npages, mmu_ap_t perms) } /* invalidate TLB */ - asm volatile("mcr p15, 0, v1, c8, c7, 0" + asm volatile("mcr p15, 0, v1, c8, c7, 0 \n\t" + "dsb \n\t" : : : "v1", "memory"); return 0;